View EVAL-AD7091RSDZ_6943846.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 msps, ultralow power, 12 - bit adc in 10 - lead lfcsp and msop data sheet ad7091r rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. te l: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features fast throughput rate of 1 msps specified for v dd of 2.7 v to 5.25 v logic voltage v drive of 1.65 v to 5.25 v inl of 1 lsb max imum analog input range of 0 v to v ref ultral ow power 3 49 a typical at 3 v and 1 msps 264 na ty pical at 3 v in power - down mode i nternal 2.5 v reference , 4.5 ppm/c typical drift wide input bandwidth flexible power/throughput rate management high speed serial interface spi?/qspi?/microwire?/dsp compatible busy indicat or power - down mode 10 - lead , 3 mm 2 mm lfcsp and 10 - lead msop package s temperature range of ? 40c to + 125c applications battery - powered systems hand held meters medical instruments mobile communications instrumentation and control systems data acquisition systems optical sensors diagnostic/monitoring functions energy harvesting functional block dia gram figure 1. figure 2 . power vs. throughput rate general description the ad7091r is a 12 - bit successive approximation analog - to - digital converter (adc) that offers ultralow power consumption (typically 349 a at 3 v and 1 msps) while achieving fast throughput rates (1 msps with a 5 0 m hz sclk). operating from a single 2.7 v to 5.25 v power supply, the part contains a wide bandwidth track - and - hold amplifier that can handle input frequencies in excess of 7 mhz. the ad7091r also features an on - chip conversion clock, accurate reference, and high speed serial interface. the conversion process and data acquisition are controlled using a convst signal and an internal oscillator. the ad 7091r has a serial interface that allows data to be read after the conversion while achieving a 1 msps throughput rate. the ad7091r uses advanced design and process techniques to achieve very low power dissipation at high throughput rates. an on - chip, accurate 2.5 v reference is available. product highlights 1. lowest power 12 - bit sar adc available. 2. on - chip, accurate 2.5 v reference. 3. hig h throughput rate with ultralow power consumption. 4. flexible power/throughput rate management. average power scales with the throughput rate. power - down mode allows the average power consumption to be reduced when the device is not performing a conversion. 5. single supply operation with v drive function. the ad7091r operates from a single 2.7 v to 5.25 v supply. the v drive function allows the serial interface to connect directly to 1.8 v to 3.3 v processors. 2.5v ref conversion contro l logic gnd clk osc v in regca p v dd 12-bit sar seria l inter f ace sdo ad7091r sclk cs v drive convst t/h ref in /ref out 10494-001 0 100 200 300 400 500 600 700 800 900 1000 1100 0 200 400 600 800 1000 power (w) throughput rate (ksps) v dd v drive v dd = v drive = 3v v dd = v drive = 3v 10494-002
ad7091r data sheet rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 11 theory of operation ...................................................................... 12 circuit information .................................................................... 12 converter operation .................................................................. 12 adc transfer function ............................................................. 12 internal/external voltage reference ........................................ 12 typical connection diagram ................................................... 13 analog input ............................................................................... 13 modes of operation ................................................................... 14 power consumption .................................................................. 14 serial int erface ................................................................................ 16 with busy indicator ................................................................. 16 without busy indicator ........................................................... 17 software reset ............................................................................. 18 interfacing with 8 - /16 - bit spi ................................................. 18 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 8 /1 2 revision 0: initial versi on
data sheet ad7091r rev. 0 | page 3 of 20 specifications v dd = 2.7 v to 5 .25 v, v drive = 1.65 v to 5.25 v, v ref = 2.5 v internal reference , f sample = 1 msps , f sclk = 5 0 m hz, t a = ?40c to +125c , unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit dynamic performance 1 f in = 10 khz sine wave signal - to - noise ratio (snr) 2 66.5 69 db f sample = 500 ksps 67.5 70 db signal - to - noise - and - distortion ratio (sinad) 2 66 6 9 db total harmonic distortion (thd) 2 ? 84 ? 7 9 db spurious free dynamic range (sfdr) 2 ? 85 ? 7 8 db aperture delay 2 5 ns aperture jitter 2 40 ps full power bandwidth 2 at ?3 db 7.5 m hz at ?0.1 db 1.2 m hz dc accuracy resolution 12 bits integral nonlinearity (inl) 2 , 3 v drive 3. 3 v 0. 8 1 lsb v drive > 3.3 v with external v ref 1 lsb differential nonlinearity (dnl) 2 guaranteed no missing codes to 12 bits 0. 3 0.9 lsb offset error 2 0.6 2 lsb gain error 2 0.8 3 lsb total unadjusted error (tue) 2 ? 2 lsb analog input input voltage range 0 v ref v dc leakage current 1 a input capacitance 4 during acquisition phase 7 pf outside acquisition phase 1 p f voltage reference in put /out put ref out 2.48 5 2.5 2.52 5 v ref in 2.7 v dd v drift 4.5 25 ppm/ c logic inputs input high voltage (v inh ) 0.7 v drive v input low voltage (v inl ) 0.3 v drive v input current (i in ) typically 10 na, v in = 0 v or v d rive 1 a input capacitance (c in ) 4 5 pf logic outputs output high voltage (v oh ) i source = 200 a v drive ? 0.2 v output low voltage (v ol ) i sink = 200 a 0.4 v floating state leakage current 1 a floating state output capacitance 4 5 pf output coding straight binary conversion rate conversion time 6 5 0 n s track - and - hold acquisition time 2 , 4 full - scale step input 350 n s throughput rate 1 m sps
ad7091r data sheet rev. 0 | page 4 of 20 parameter test conditions/comments min typ max unit power requirements v dd 2.7 5.25 v v drive 1.65 5.25 v i dd v in = 0 v normal mode static 5 v dd = 5 .25 v 22 60 a v dd = 3 v 2 1.6 33 a normal mode operational v dd = 5 .25 v , f sample = 1 msps 3 88 4 49 a v dd = 3 v , f sample = 1 msps 3 49 4 08 a v dd = 3 v , f sample = 100 ksps 55 a power - down mode v dd = 5 .25 v 0. 334 4 . 4 a v dd = 5.25 v, t a = ?40c to + 8 5c 0. 334 1.4 a v dd = 3 v 0. 264 4 . 2 a v dd = 3 v, t a = ?40c to + 8 5c 0. 264 1.2 a i drive v in = 0 v normal mode static 6 v d rive = 5 .25 v 32 500 n a v d rive = 3 v 28 500 n a normal mode operational v d rive = 5 .25 v , f sample = 1 msps 42 86 a v d rive = 3 v , f sample = 1 msps 1 7 20 a power - down mode v d rive = 5 .25 v 7 4 1 na v d rive = 3 v 2 28 na total power dissipation ( p d d + p drive ) v in = 0 v normal mode static 5 v dd = v d rive = 5 .25 v 116 318 w v dd = v d rive = 3 v 65 101 w normal mode operational v dd = v d rive = 5 .25 v , f sample = 1 msps 2. 3 2. 9 mw v dd = v d rive = 3 v , f sample = 1 msps 1 1.3 m w power - down mode v dd = v d rive = 5 .25 v 1 . 8 24 w v dd = v d rive = 3 v 0. 8 13 w 1 dynamic performance is achieved with a burst sclk. operating a free running sclk during acquisition phase degrades dynamic pe rformance. 2 see the terminology section. 3 for v d rive < v d d + 0.7 v . 4 sample tested during initial release to ensure compliance. 5 sclk is operating in burst mode and cs is idling high. with a free running sclk and cs pulled low, the i dd static current is increased by 3 0 a typical at v dd = 5.25 v. 6 sclk is operating in burst mode and cs is idling high. with a free running sclk and cs pulled low, the i drive static current is increased by 3 2 a typical at v drive = 5.25 v.
data sheet ad7091r rev. 0 | page 5 of 20 timing specifications v dd = 2 .75 v to 5.25 v, v drive = 1.65 v to 5.25 v, t a = ?40c to +125c , unless otherwise noted. 1 table 2 . parameter limit at t min , t max unit description f sclk 5 0 mhz max frequency of serial read clock t 1 8 ns max delay from the end of a conversion until sdo three - state is disabled t 2 7 ns max data access time after sclk falling edge t 3 0.4 t sclk ns min sclk high pulse width t 4 3 ns min sclk to data valid hold time t 5 0.4 t sclk ns min sclk low pulse width t 6 15 ns max sclk falling edge to sdo high impedance t 7 10 ns min convst pulse width t 8 6 5 0 ns max conversion time t 9 6 ns min cs low time before the end of a conversion t 10 18 ns max delay from cs until sdo three - state is disabled t 11 8 ns min cs high time before the end of a conversion t 12 8 ns min delay from the end of a conversion until cs falling edge t 13 50 m s typ power - up time with internal reference 2 100 s max power - up time with external reference t quiet 50 ns min time between last sclk edge and next convst pulse 1 sample tested during initial release to ensure compliance. 2 with a 2.2 f reference capacitor.
ad7091r data sheet rev. 0 | page 6 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted . table 3 . parameter rating v dd to gnd ?0.3 v to + 7 v v drive to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v ref + 0.3 v digital input voltage to gnd ?0.3 v to v drive + 0.3 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c esd hbm 2.5 kv ficdm 1.5 kv 1 transient currents of up to 100 ma do not cause silicon controlled rectifier ( scr ) latch - u p. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 4 . thermal resistance package type ja jc unit 10 - lead lfcsp 3 3 . 2 4 c/w 10 - lead msop 25.67 1.67 c/w esd caution
data sheet ad7091r rev. 0 | page 7 of 20 pin configuration an d function descripti ons figure 3 . pin configuration , 10 - lead lfcsp figure 4 . pin configuration , 10 - lead msop table 5 . pin function descriptions pin no. lfsp sop nemonic description 1 1 v dd power supply input. the v dd range is from 2.7 v to 5.25 v. this supply pin should be decoupled to gnd. t he t ypical recommended values are 10 f and 0.1 f. 2 2 ref in /ref out voltage reference input output. decouple this pin to gnd. t he t ypical recommended decoupling capacitor value is 2.2 f. the user can either access the internal 2.5 v reference or overdrive the internal reference with an externally applied voltage. the reference vo ltage range for an externally applied reference is 2.7 v to v dd . 3 3 v in analog input. the single - ended analog input range is from 0 v to v ref . 4 4 regcap decoupling capacitor pin for voltage output from internal regulator. this output pin should be decoupled separately to gnd using a 1 f capacitor. the voltage at this pin is 1.8 v typical. 5 5 gnd analog ground. this pin is the ground reference point for all circuitry on the ad7091r . the analog input si gnal should be referred to this gnd voltage. 6 6 convst convert start. active low edge triggered logic input. the falling edge of convst places the track - and - hold into hold mode and initiates a conversion. 7 7 cs chip select. active low logic input. the serial bus is enabled when cs is held low, and in this mode cs is used to frame the output data on the spi bus. 8 8 sclk serial clock. this pin acts as the serial clock input. 9 9 sdo serial data output. the conversion output data is supplied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data is provided msb first. 10 10 v drive logic power supply input. the voltage supplied at this pin determines the operating voltage of the interface. decoupling capacitors should be connected between v drive and gnd. t he t ypical recommended values are 10 f and 0.1 f. the voltage range of this pin is 1.65 v to 5.2 5 v. 11 n/a epad exposed pad. the exposed pad is not connected internally. for increased reliability of the solder joints and for maximum thermal capability, solder the exposed pad to the substrate, gnd. notes 1. the exposed p ad is not connected internal l y . for increased reliabilit y of the solder joints and for maximum therma l ca p abilit y , solder the exposed p ad t o the substr a te, gnd. ad7091r 1 v dd 2 ref in /ref out 3 v in 4 regca p 5 gnd 10 v drive 9 sdo 8 sclk 7 cs 6 convst t op view (not to scale) 10494-003 v dd ref in /ref out v in regca p gnd v drive sdo sclk cs convst 1 2 3 4 5 10 9 8 7 6 ad7091r t op view (not to scale) 10494-004
ad7091r data sheet rev. 0 | page 8 of 20 typical performance characteristics figure 5. typical dynamic performance figure 6. typical inl performance figure 7 . typical dnl performance figure 8. snr vs. analog input frequency for various supply voltages figure 9. t hd vs. analog input frequency for various supply voltages figure 10 . t hd vs. source impedance ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 snr (db) frequenc y (khz) v d d = 2.7v v dr i ve = 3.3v t a = 25c f in = 10 k h z f s a mp l e = 1 m s p s s n r = 69 . 32db s i n a d = 68.66db t hd = ?84 . 42db 10494-005 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 in l (lsb) code 10494-006 v d d = 2.7v v dr i ve = 3.3v t a = 25c f s a mp l e = 1 m s p s ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 dn l (lsb) code v d d = 2.7v v dr i ve = 3.3v t a = 25c f s a mp l e = 1 m s p s 10494-007 60 62 64 66 68 70 72 1 10 100 snr (db) input frequenc y (khz) t a = 25c 2 . 7 v 3.0v 5.0v 10494-008 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 thd (db) input frequenc y (khz) t a = 25c f sample = 1msps 2. 7 v 3.0v 5.0v 10494-009 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 10 100 1k 10k thd (db) source impedance () 10494-010 t a = 25c v dd = 3v f i n = 10 k h z f sample = 1m s p s
data sheet ad7091r rev. 0 | page 9 of 20 figure 11. sinad vs. analog input frequency for various supply voltages figure 12. histogram of codes at code cent e r (v ref /2) figure 13. t sdo dela y vs. sdo capacitance load and v drive figure 14 . reference voltage output vs. current load for various temperatures figure 15 . operational i dd supply current vs. v d d supply voltage for various temperatures figure 16 . operational i drive supply current vs. v driv e supply voltage for various temperatures 60 62 64 66 68 70 72 1 10 100 sinad (db) input frequenc y (khz) t a = 25c 2 . 7 v 3.0v 5.0v 10494-0 1 1 60 50 10 20 30 40 0 2046 2050 2049 2048 2047 number of occurrences (k) code 10494-012 v dd = v drive = 3v 65k samples t a = 25c 53423 5655 6458 0 2 4 6 8 10 12 10 20 30 40 50 t sdo del a y (ns) sdo ca p aci t ance load (pf) v dr i ve = 3v , ?40c v dri ve = 3v , +25c v dr i ve = 3v , +125c v dr i ve = 1. 8v , +125c v dr i ve = 1. 8v , +25c v dr i ve = 1. 8v , ?40c 10494-013 2.484 2.486 2.488 2.490 2.492 2.494 2.496 2.498 2.500 2.502 0 20 40 60 80 100 v ref (v) current load (a) + 25 c ?40 c + 85 c + 125 c v dd = v drive = 3v 10494-014 450 250 2.7 i dd supply current (a) v dd supply voltage (v) 10494-015 270 290 310 330 350 370 390 410 430 3.2 3.7 4.2 4.7 5.2 f sample = 1msps ?40 c + 25 c + 85 c + 125 c 90 0 1.65 2.65 3.65 4.65 i drive supply current (a) v drive supply voltage (v) 10494-031 10 20 30 40 50 60 70 80 f sample = 1msps v in = 0v ?40 c + 25 c + 85 c + 125 c
ad7091r data sheet rev. 0 | page 10 of 20 figure 17 . total power - down supply current (i dd and i driv e ) vs. temperature for various supply voltages 4000 0 ?40 25 85 125 total current (na) operating temperature (c) 10494-032 500 1000 1500 2000 2500 3000 3500 v dd = 3v, v drive = 3v v dd = 5v, v drive = 5v v dd = 5v, v drive = 3.3v
data sheet ad7091r rev. 0 | page 11 of 20 terminology integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. for the ad7091r , the endpoints of the transfer function are zero scale ( a point 0.5 lsb below the first code transition ) and full scale ( a point 0.5 lsb above the last code transition ) . differential nonlinearity (dnl) d nl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error offset error is the deviation of the first code transition (00 ... 000) to (00 .. . 001) from the ideal (such as gnd + 0.5 lsb). ga in error gain error is the deviation of the last code transition (111 .. . 110) to (111 . . . 111) from the ideal (such as v ref ? 1.5 lsb) after the offset error has b een adjusted out. track - and - hold acquisition time the tra ck - and - hold amplifier returns to track mode after the end of a conversion. t he t rack - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 0.5 lsb, after a conversion (s ee the serial interfa ce section for more details ) . signal -to - noise ratio (snr) sn r is the measured ratio of signal to noise at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequen cy ( f sample /2), excl uding dc. the ratio is dependent on the number of quantization levels in the digitization process : the more levels, the smaller the quantization noise. the theoretical signal - to - noise ratio for an ideal n - bit converter with a sine wave input is given by signal - to - noise ratio = ( 6.02 n + 1.76 ) db therefore , for a 12 - bit convert er, the snr is 74 db. signal -to - noise - and - distortion ratio (sinad) sinad is t he measured ratio of signal to noise and distortion at the output of the adc. the signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s ample /2), including harmonics, but excluding dc. total unadjusted error (tue) tue is a comprehensive specification that includes the gain, linearity , and offset errors. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7091r , thd is defined as ( ) 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 db + + + + = w here : v 1 is the rms amplitude of the fundamental . v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. spurious free dynamic range (sfdr) sfdr, also known as peak harmonic or spurious noise , is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f sample /2 and excluding dc) to the rms value of the fundamental. usually , the value of this specif i - cation is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, the largest harmonic would be a noise peak. aperture delay aper ture delay is t he measured interval between the leading edge of t he sampling clock and the point at which the adc sample s data . aperture jitter aperture jitter is the sample - to - sample variation in the effective point in time at which the data is sample d . full power bandwidth full power bandwidth is t he input frequency at which the amplitude of the reconstructe d fundamental is reduced by 0.1 db or 3 db for a full - scale input.
ad7091r data sheet rev. 0 | page 12 of 20 theory of operation circuit information the ad7091r is a 12 - bit successive approximation analog - to - digital converter (adc) that offers ultralow power consumption (typically 3 49 a at 3 v and 1 msps) while achieving fast throughput rates (1 msps with a 5 0 mhz sclk) . the part can be operated from a single power supply in the range of 2.7 v to 5.25 v. the ad7091r provides an on - chip track - and - hold adc with a seria l interface housed in a tiny 10 - lead lfcsp and 10 - lead msop package s . th e s e package s offer considerable space - saving advantages compared with alternative solutions. the serial clock input accesses data from the part. the clock for the successive approximation adc is generated internally. the reference voltage for the ad7091r is generated internally by an accurate on - chip reference source. the analog input range for the ad7091r is 0 v to v ref . the ad7091r also features a power - down option to save power between conversions. the power - down feature is implemented across the standard serial interface as described in the modes of operation section. converter operation the ad7091r is a successive approximation adc based around a charge redistribution dac. figure 18 and figure 19 show simplified schematics of the adc. figure 18 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the s ignal on v in . figure 18 . adc acquisition phase w hen the adc starts a conversion , sw2 opens and sw1 moves to position b (see figure 19) , causing the comparator to become unbalanced. the contro l logic and the charge redistri bution dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring th e comparator back into a balanced conditio n. when the comparator is rebal anced, the conversion is complete. the control logic generates the adc output code. figure 20 show the ideal adc transfer function. figure 19 . adc conversion phase adc transfer functio n the output coding of the ad7091r is straight binary. the designed code transitions occur midway between successive integer lsb values, such as 0.5 lsb, 1 .5 ls b , and so on. th e lsb size for the ad7091r is v ref /4096. the ideal transfer characteristic s for the ad7091r are shown in figure 20 . figure 20 . ad709 1r ideal transfer characteristic s internal/external voltage reference the ad7091r allows the choice of a n internal voltage reference or an external voltage reference. the internal reference provides an accurate 2.5 v low temperature drift voltage reference. the internal reference is available at the ref in /ref out pin . when using the internal reference , t his pin should be decoupled using a capacitor with a typical value of 2.2 f to achieve the specified performan ce . with a fully discharged 2.2 f reference capacitor , the internal reference requires 50 ms typically to fully charge to the 2.5 v ref out voltage level. in power - down mode , the internal voltage reference is shut down . after exiting power - down mode , a dequate time should be allowed for the reference capacitor to recharge before performing a con - version. the time required to recharge the reference capacitor is dependent on the amount of charge remaining on the capacitor when exiting power - down mode. if t he on - chip reference is used ex ternally to the ad7091r , it is recommended to buffer this reference before supplying the external circuitry. alternatively, the ad7091r reference voltage can be applied externally. if an external reference is applied to the device, the internal referenc e is automatically overdriven. an e xternally applied reference voltage should be in the range of 2.7 v to 5.25 v and should be conn ected to the ref in /ref out pin. charge redistribution dac control logic comparator sw2 sampling capacitor acquisition phase sw1 a b gnd ldo/2 v in 10494-017 charge redistribution dac control logic comparator sw2 sampling capacitor conversion phase sw1 a b gnd ldo/2 v in 10494-018 000 ... 000 0v adc code analog input 111 ... 111 000 ... 001 000 ... 010 111 ... 110 111 ... 000 011 ... 111 1lsb v ref ? 1lsb 1lsb = v ref /4096 10494-019
data sheet ad7091r rev. 0 | page 13 of 20 typical connection d iagram figure 22 shows a typical connection diagram for the ad7091r . a positive power supply in the range of 2.7 v to 5.25 v should be connected to the v dd pin, with typical values for decoupling capacitors being 100 nf and 10 f. these capacitors should be placed as close as possible to the device pins. wit h the power supply connected to the v dd pin, t he ad7091r operates with the internal 2.5 v reference , and t he ref in /ref out pin should be decoupled using a capacitor with a typical value of 2.2 f to achieve the specified performance and provide an analog input range of 0 v to v ref . t he t ypical value for the regulator bypass decoupling capacitor (regcap) is 1 f. the voltage applied to the v drive input controls the voltage of the serial interface ; therefore , this pin should be connected to the supply voltage of the microprocessor. v drive can be set in the range of 1.65 v to 5.25 v. typical values for the v drive decoupling capacitors are 100 nf and 10 f. the conversion result is output in a 12 - bit word with the msb first. the ad7091r requires the user to initiate a software reset upon power - up (see the software reset section). if an external reference is applied to the device, the internal referenc e is automatically overdriven. an e xternally applied reference voltage should be in the range of 2.7 v to 5.25 v and should be connected to the ref in /ref out pin. if the busy indicat or fe ature is required , a pull - up resistor of typically 100 k to v drive should be connected to the sdo pin. in addition, f or applications in which power consumption is a concern, the power - down mode can be used to improve the power performance of the adc (s ee the modes of operation section for more details ) . analog input figure 21 shows an equivalent circuit of the ad7091r analog input structure . the d1 and d2 diodes provide esd protection for the analog input. the d3 diode is a parasitic diode between v in and v ref . to pre ve nt the diodes from becom ing forward - biased and from start ing to conduct current , ensure that the analog input signal never exceeds v ref or v dd by more than 300 mv. these diodes can conduct a maximum of 10 ma without causing irreversible damage to the part. figure 21 . equivalent analog input circuit capacitor c1 in figure 21 is typically about 1 p f and can primarily be attributed to pin capacitance. resistor r1 is a lumped component made up of the on resistance of a switch. this resistor is typically about 500 . capacitor c2 is the adc sampling capacitor and ty pically has a capacitance of 3.6 p f. in applications where harmonic distortion and signal - to - noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this may necessitate using an input buffer amplifier as shown in figure 22 . the choice of the op amp is a function of a particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd in creases as the source impedance increases and performance degrades. figure 10 shows a graph of thd vs. source impedance when using a supply voltage of 3 v and a sampling rate of 1 msps. u se an external filter such as a one - pole, low - pass rc filter, or similar, as shown in figure 22 o n the analog input connected to the ad7091r to achi eve the spe cified performances. figure 22 . ad7091r typical connection diagram d1 d2 r1 c2 3.6pf v dd v in c1 1pf c3 2.5pf notes 1. during the conversion phase, the switch is open. during the track phase, the switch is closed. d3 v ref 10494-021 ad7091r sclk sdo microprocessor/ microcontroller/ dsp cs v in gnd v dd 10f 100nf 10f 100nf regcap 1f convst 2.2f analog input 51 4.7nf 100k with busy indication v drive 2.7v to 5.25v 1.65v to 5.25v v drive ref in / ref out 10494-020
ad7091r data sheet rev. 0 | page 14 of 20 modes of operation the mode of operation of the ad7091r is selected by controlling the logic state of th e convst signal when a conversion is complete. the logic level of the convst pin at the end of a conversion determines whether the ad7091r remain s in normal mode or enters power - down mode (see the normal mode and power - down mode sections) . similarly, if the device is already in power - down mode , convst controls whether the device returns to normal mode or remains in power - down mode . these modes of operation provide flexible power management options , allowing op timization of the ratio of the power dissipation to the throughput rate for different application requirements. normal mode th e normal mode of operation is intended to achieve the fastest throughput rate performance. users do not have to worry about power - up times because the ad7091r remain s fully powered at all times. figure 29 shows the general timing diagram of the ad7091r in normal mode. in this mode, t he conversion is initiated on the falling edge of convst , as desc ribed in the serial interface s e c ti on. to ensure that the part remains fully powered up at all times, convst must return high after t 7 and remain high until the conversion is com plete . at the end of a conversion (denot ed as eoc in figure 27 ), the logic state of convst is tested. to read back data stored in the conversion result register , wait until the conversion is complete , and then pull cs low . t he conversion data is subsequently clocked out on the sdo pin (see figure 29 ) . because t he output shift register is 12 bit s wide , d ata is shifted out of the device as a 12 - bit word under the co ntrol of the serial clock input ( sclk ) . after reading back the data , the us er can pull convst low again to start another conversion after the t quiet time has elapsed. power - down mode th e power - down mode of operation is intended for use in applications where slower throughput rates and lower power consumption are required. in this mode, the adc can be powered down either between each conversion or between a series of conversio ns performed at a high throughput rate , with the adc powered down for relatively long duration s between these bursts of several conversions. when the ad7091r is in power - down mode, the serial interface remains active even though all a nalog circuitry , including the internal voltage reference , is powered d own. to enter power - down mode , pull convst low and keep it low until the end of a conversion (denoted as eoc in figure 30 ) . after the conversion is complete , the logic level of the convst pin is tested. if the convst signal is logic low at th is point, the part enters power - down mode. the serial interface of the ad7091r i s functional in power - down mode; therefore , users can read back the conversion result after the part enters power - down mode. to exit this mode of operation and power up the ad7091r , pull convst high at any time. on the rising edge of convst , the device begins to power up. the i nternal circuitry of t he ad7091r requires 100 s to power up from power - down mode . if the internal reference is used, t he reference capacitor must be fully recharged before accurate conversions are possible . t o start the next conversion after exiting power - down mode , operate the interface as described in the normal mod e section. power consumption the two modes of operation for the ad7091r normal mode and power - down mode (see the modes of operation section for more information ) produce different power vs. throughput rate performances. using a combination of normal mode and power - down mode achieves the optimum power perform ance. to calculate the overall power consumption , the i drive current should also be taken into consideration. figure 16 shows the i drive current at various supply voltages. figure 23 and figure 24 show the power consumption for v drive with various throughput rates. improved power consumption for the ad7091r can be achieved by careful ly selectin g the v dd and v drive supply voltages and the sdo line capacitance (see figure 15 and figure 16) . normal mode with a 3 v v dd supply and a throughput rate of 1 msps , the i dd current consumption for the part in normal operational mode is 3 49 a (composed of 2 1.6 a of static current and 3 2 7.4 a of dynamic current during conversion ) . the d ynamic current consumption is directly proportional to the throughput rate . the following example calculates the power consumption of ad7091r when operating in normal mode with a 500 ksps throughput rate and a 3 v supply. t he dynamic conversion time con tributes 49 1 w to the overall power dissipation as follows : (( 500 ksps / 1 msps ) 3 27.4 a ) 3 v = 49 1 w the contribution to the total power dissipated by the n ormal mode static operation is 2 1.6 a 3 v = 6 5 w therefore, the total power dissipated at 500 ksps is 491 w + 6 5 w = 55 6 w
data sheet ad7091r rev. 0 | page 15 of 20 normal and power - down mode combination a combination of normal mode and power - down mode achieves the optimum power performance. the internal circuitry of the ad7091r requires 100 s to power up from power - down mode . power - down mode can therefore be performed at sampling rate s of less than 10 k sps . r echarging the reference capacitor should also be considered when using the on - chip reference . the ad7091r can fully charge a 2.2 f reference capacitor in typically 50 ms . however , t he time to charge the reference capacitor is dependent on the amount of charge remaining on the capacito r when exiting power - down mode. the reference capacitor lose s charge very slowly , resulting in much faster recharge times. figure 25 shows the ad7091r conversion sequence with a combination of normal mode and power - down mode with a throughput of 5 k sps when using an external reference . with a v dd supply voltage of 3 v , the static current is 2 1.6 a. the dynamic current is 3 2 7.4 a at 1 msps. the current consumption during power - down mode is 2 6 4 na. a convers ion requires 6 5 0 ns to complete , and the ad7091r requires 1 00 s to power up from power - down mode when using an external reference . the dynam ic conversion time contributes 4. 9 w to the overall power dissipation as follows : ( ( 5 k sps/ 1 m sps ) 3 2 7.4 a ) 3 v = 4 .9 w the contributi on to the total power dissipated by the normal mode static operation and power - down mode is ((1 00.6 s/2 00 s) 2 1.6 a) 3 v + (( 99.4 s/ 2 00 s) 26 4 na) 3 v = 3 3 w the conversion time of 6 5 0 ns is included in the static opera - tion time. the total power dissipated at 5 k sps is 4 .9 w + 3 3 w = 3 7.9 w figure 23 and figure 24 show the typical power vs. throughput rate for the ad7091r at 3 v for the v dd supply and for the v drive supply . power consumption for the v drive supply can be calculated by the same principles as those for the v dd supply. additionally , figure 24 shows the reduction in power consumption that can be achiev ed when power - down mode is used compared with using only normal mode at lower throughput rate s. figure 23 . powe r dissipation vs. thro ughput rate (full range) figure 24 . pow er dissipation vs. t hroughput rate (lower range) figure 25 . 10 sps with normal and power - down mode 0 100 200 300 400 500 600 700 800 900 1000 1100 0 200 400 600 800 1000 power (w) throughput rate (ksps) v dd v drive v dd = v drive = 3v v dd = v drive = 3v 10494-016 0.001 0.01 0.1 1 10 1000 100 0.01 0.1 1 100 10 power (w) throughput r a te (ksps) 10494- 1 17 v dd = v drive = 3v v in = 0v external reference v dd ( n o p d) v drive ( n o p d) v dd v drive 99s power-down 100s power-u p 650ns conversion convst eoc cs sdo dat a 200s 10494-022
ad7091r data sheet rev. 0 | page 16 of 20 serial interface the ad7091r serial interface consists of four signals: sdo, sclk, convst , and cs . the serial interface is use d for accessing data from the result register and controlling the modes of operation of the device. sclk is the serial clock input for the device , and sdo data transfers take place with respect to this sclk. the convst signal is used to i nitiate the conversion process and to select the mode of operation of the ad7091r ( see the modes of operation section ) . cs is used to frame the data. the falling edge of cs takes the sdo line out of a high impedance state. a rising edge on cs retu rns the sdo to a high impedance state. the logic level of cs at the end of a conversion determines whether the busy indicator feature is enabled. this feature affect s the propagation of the ms b with respect to cs and scl k. with busy indicator when the busy indicator feature is enabled , the sdo pin can be used as an interrupt signal to indicate that a conversion is complete. the connection diagram for this configuration is shown in figure 26 . note that a pull - up resistor to v drive is required on the sdo pin. this allows the host to detect when the sdo pin exits the three - state condition after the end of a conve rsion. in this mode , 13 sclk cycles are required : 12 clock cycle s to propagate out the data an d an additional clock cycle to re turn the sdo pin to the three - state condition. to enable the busy indicat or feature , a conversion should first be started. a high - to - low transition on convst initiates a conversion. this puts the track - and - hold into hold mode and samples the analog input at this point. if the user does not want the ad7091r to enter power - down mode, convst should be taken high before the end of the conversion. a conversion requ ires 6 5 0 ns to complete. when the conversion process is finished, the track - and - hold goes back to track mode. before the end of a conversion , pull cs low to enable the busy indicator feature. the conversion result is shifted out of the device as a 12 - bit word under the control of sclk and the logic state of cs at the end of a conversion . at the end of a conversion , sd o is driven low. sdo remain s low until the msb (db11) of the conversion result is clocked out on the first falling edge of sclk. db10 to db0 are shifted out on the subsequent falling edges of sclk. the 13 th sclk falling edge return s sdo to a high impedance state. data is propagated on sclk falling edges and is valid on both the rising and falling edges of the next sclk . the timing diagram for this mode is shown in figure 27 . if another conversion is required, pull convst lo w again an d repeat the read cycle. figure 26 . connection diagram with busy indicator figure 27 . serial p ort timing with busy indicator data in irq clk convert v drive digital host 100k? convst sclk sdo cs ad7091r cs1 10494-025 t hr ee-st a t e t hr ee-st a t e c s sc l k 1 5 1 2 2 3 4 db 1 1 db 10 db 9 db 2 db 1 db 0 t 2 t 4 t 3 t 5 t 6 db 8 db 7 sdo convst eoc notes 1. eoc is the end of a conversion. t 1 1 0 1 1 t 9 t quiet t 7 t 8 1 3 10494-026
data sheet ad7091r rev. 0 | page 17 of 20 without busy indicator to operate the ad7091r without the busy indicat or feature enabled, a conversion should first be started. a high - to - low transition on convst initiates a conversion. this puts the track - and - hold into hold mode and samples th e analog input at this point. if the user does not want the a d7091r to enter power - down mode, convst should be taken high before the end of the conversion. a conversion requires 6 5 0 ns to complete. when the conversion process is finished, the track - and - hold goes back to track mode. to prevent the busy indicator feature from becoming enabled , ensure that cs is pulled high before the end of the conversion. the data is shifted out of the device as a 12 - bit word under the control of sclk and cs . the msb ( bit db 11 ) is clocked out on the falling edge of cs . db10 to db0 are shifted out on the subsequent falling edges of sclk. t he 12 th falling sclk edge returns sdo to a high impedance state. after all the data is clocked out , pull cs high again. sclk should idle low in this mode to ensure that the msb is not lost. data is propagated on sclk fallin g edges and is valid on both the rising and falling edges of the next sclk. the timing diagram for this operation is shown in figure 28 . if another conversion is required, pull convst low and repeat the read cycle. figure 28 . serial port timing without busy indicator t hr ee-st a t e t hr ee-st a t e c s sc l k 1 5 1 2 2 3 4 db11 db 10 db 9 db 2 db 1 t 2 t 3 t 5 t 6 db 8 db 7 sdo convst eoc 1 0 1 1 t 10 t quiet t 7 t 8 t 4 t 11 db 0 t 12 10494-027 notes 1. eoc is the end of a conversion.
ad7091r data sheet rev. 0 | page 18 of 20 software reset the ad7091r requires the user to initiate a software reset when power is first applied . it should be noted that failure to apply the correct software reset command may resul t in a device malfunction . t o issue a software reset , 1. start a conversion . 2. r ead back the conversion result by pulling cs low a fter the conversion is complete. 3. between the second and eighth sclk cycles, pull cs high to short cycle the read operation. 4. a t th e end of the next conversion , the sof tware reset is executed. if using the on - chip in ternal reference , the user should wait until the reference capacitor is fully charged to meet the specified performance. the timing diagram for this operation is shown in figure 31. interfacing w ith 8 - / 16 - bit spi it is also possible to interface the ad7091r with a conventional 8 - / 16- bit spi bus. performing conversions and reading results can be achieved by configuring the host spi interface to 16 bits , which results in providing an additional four sclk cycles to complete a conversion compared with the standard interface methods ( see the with busy indicator and without busy indicator sections). after the 1 3 th sclk falling edge with the busy indicator feature enabled or the 1 2 th sclk falling edge with the busy indicator feature disabled , sdo returns to a high impedance state . the additional four bits shou ld be treated as dont care s by the host. all other timings are as outlined in figure 27 and figure 28, with t quiet starting after the 16 th sclk cycle. a software reset can be performed by configuring the spi bus to eight bits and performing the operation outlined in the software reset section. figure 29 . serial interface read timing normal mode figure 30 . entering/exiting power - down mode notes 1 . don?t care. t 8 convst t 7 conversion data t 10 cs sdo eoc t 12 10494-028 2. eoc is the end of a conversion. t 8 convst conversion data t 10 cs sdo eoc power-down mode t 12 t 13 notes 1 . don?t care. 10494-029 2. eoc is the end of a conversion.
data sheet ad7091r rev. 0 | page 19 of 20 figure 31 . software reset timing t 8 convst t 7 short cycle read t 10 t 3 t 5 cs sdo eoc eoc/ software reset t 12 t 8 t 7 10494-030 sc l k 1 2 8 7 6 notes 1. don?t care. 2. eoc is the end of a co n version.
ad7091r data sheet rev. 0 | page 20 of 20 o utline d imensions figure 32 . 10 - lead lead frame chip scale package [lfcsp _wd ] 3 mm 2 mm body, very very thin, dual lead (cp - 10 - 12) dimensions shown in millimeters figure 33 . 10 - lead mini small outline package [ msop ] (rm - 10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ad7091r bcpz - rl ?40c to +125c 10 - lead lead frame chip scale package [lfcsp _wd ] cp - 10 - 12 c7 p ad7091r bcpz - rl7 ?40c to +125c 10 - lead lead frame chip scale package [lfcsp _wd ] cp -10 -12 c7 p ad7091rbrmz ?40c to +125c 10 - lead mini small outline package [ msop ] rm -10 drq ad7091rbrmz -rl7 ?40c to +125c 10 - lead mini small outline package [ msop ] rm -10 drq eval - ad7091rsdz evaluation board eval - sdp - cb1z evaluation controller board 1 z = rohs compliant part. 2.5 4 2.44 2.34 0. 35 0.3 0 0.25 t op view 1 0 1 6 5 0.3 0 0 .25 0.20 b o t t o m v i e w pin 1 ind ex ar ea sea tin g pla ne 0.80 0.75 0. 70 0.2 03 ref 0.0 5 max 0.02 nom 0.50 bsc 2.10 2.0 0 1. 90 3. 10 3.0 0 2.90 e x p o s e d p a d pin 1 indica t or (r 0.15 ) for pro per con ne cti on of the ex pos ed pad, refer to the pin confi gurat ion and funct ion des cri pti on s sec tio n of th is dat a she et. 1.00 0.9 0 0. 80 compl i ant t o jedec sta nda rds mo- 229 -wc ed- 3 05- 06-2 010- b compl iant to jedec standar ds mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 m ax 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 ident ifier 15 max 0.95 0.85 0.75 0.15 0.05 ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10494 - 0 - 8/12(0)

▲Up To Search▲

Price & Availability of EVAL-AD7091RSDZ

	To Download EVAL-AD7091RSDZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .